1. Field of the Invention
The present invention relates generally to signal processing, and more particularly to accurate detection of phase differences between two signals.
2. State of the Art
Phase detector circuits are well known. For example, known circuits include combinations of phase detectors and charge pumps for detecting a phase difference between two clock-type signals and for providing an output proportional to the detected phase difference. Conventional three-state phase detector circuits which include phase detectors and charge pumps are often used in phase-locked-loop circuits. For example, a document entitled "Charge-Pump Phase-Lock Loops", by Floyd M. Gardner, IEEE Transactions On Communications, Vol. Com-28, No. 11, November 1980, pp. 1849-1858 describes a three-state charge pump. For example, the third paragraph on page 1850 of this document describes a three-position electronic switch controlled by three states of a phase/frequency detector (PFD).
Conventional phase-locked-loop circuits that use three-state phase detectors include an inherent dead-band at operation either in or near a phase locked condition. In the dead-band region, slight phase differences between the two clock-type signals cannot be detected. As the phase error of the phase-locked-loop circuit approaches zero, the phase detector no longer responds to the phase difference between the two signals and, in this sense, is dead in responding to a phase error between the signals. The dead-band is a result of limitations of circuit elements used to provide the phase-locked-loop circuit; that is, circuits composed of ideal elements would not exhibit such a dead-band.
The dead-band region of a conventional phase-locked-loop circuit that uses a three-state phase detector poses several significant drawbacks. For example, one effect of dead-band in a phase-locked-loop circuit is an uncorrectable jitter in a clock signal derived from a voltage controlled oscillator (VCO). When a near zero phase error condition exists, the absence of feedback in the phase-locked-loop circuit renders the VCO input, and thus its output, uncontrolled (i.e., a floating input). As the VCO output changes, the control loop of the phase-locked-loop circuit is unable to detect any change until the phase error exceeds the limits of the dead-band. The resultant jitter is intolerable in many applications, particularly where the phase-locked-loop circuit is used for frequency synthesis.
One approach to address the dead-band of a three-state phase detector in a phase-locked-loop circuit is to force the phase detector to operate outside its dead-band region. For example, a constant phase error term can be introduced into the phase detector as described in U.S. Pat. No. 5,036,216 (Hohmann et al), the disclosure of which is hereby incorporated by reference in its entirety. This patent describes the use of a constant phase error to ensure that phase detection circuitry produces a minimum jitter in the generated clock signal during a phase locked condition. Although the circuitry described in this patent is suitable for some applications (e.g, frequency synthesis), the disclosed system is unsuitable for high precision applications such as clock and data recovery, wherein the introduction of a fixed phase error would be detrimental to circuit operation.
Another approach for addressing the dead-band of a three-state phase detector is described in U.S. Pat. No. 4,322,643 (Preslar) the disclosure of which is hereby incorporated by reference. The phase comparator disclosed in the Preslar patent is a digital phase comparator which is effectively operated outside its dead-band.
The Preslar patent discloses a phase comparator 11 which includes an input terminal "V" for receiving a feedback signal from an output of voltage controlled oscillator 20. A second input "R" of phase comparator 11 receives a reference signal from a source 10. For each cycle of the reference signal, the phase comparator 11 produces pulsed output signals on terminals D and U proportional to any phase error between the input signals. The D and U pulses are used to drive charge pumps 16 and 14, respectively. The charge pumps drive the voltage controlled oscillator 20 via an integrator 8. As described at column 5, lines 25-31, a dead-band can occur if output pulses of the D and U terminals are shorter than turn-on times of charge pumps 14 and 16. Accordingly, column 5, lines 51-63 describe adding sufficient time duration to the U and D pulses to overcome the minimum turn-on time of the charge pumps. Thus, the Preslar patent discloses a circuit which, in accordance with ideal operation, would operate outside a dead-band. However, no practical way is disclosed to accurately tune a practical implementation of the circuit to compensate phase errors introduced during operation or to provide a desired phase offset.